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1 rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation sp3223/3243 intelligent +3.0v to +5.5v rs-232 transceivers the sp3223 and sp3243 products are rs-232 transceiver solutions intended for portable or hand-held applications such as notebook and palmtop computers. the sp3223 and sp3243 use an internal high-efficiency, charge-pump power supply that requires only 0.1 f capacitors in 3.3v operation. this charge pump and sipex's driver architecture allow the sp3223/ sp3243 series to deliver compliant rs-232 performance from a single power supply ranging from +3.3v to +5.0v. the sp3223 is a 2-driver/2-receiver device, and the sp3243 is a 3-driver/5-receiver device ideal for laptop/notebook computer and pda applications. the sp3243 includes one complementary receiver that remains alert to monitor an external device's ring indicate signal while the device is shutdown. the auto on-line feature allows the device to automatically "wake-up" during a shutdown state when an rs-232 cable is connected and a connected peripheral is turned on. otherwise, the device automatically shuts itself down drawing less than 1 a. meets true eia/tia-232-f standards from a +3.0v to +5.5v power supply interoperable with eia/tia-232 and adheres to eia/tia-562 down to a +2.7v power source auto on-line circuitry automatically wakes up from a 1 a shutdown minimum 120kbps data rate under load regulated charge pump yields stable rs-232 outputs regardless of v cc variations esd specifications: +2kv human body model description selection table applicable u.s. patents - 5,306,954; and other patents pending. e c i v e ds e i l p p u s r e w o p2 3 2 - s r s r e v i r d 2 3 2 - s r s r e v i e c e r l a n r e t x e s t n e n o p m o c e n i l - n o o t u a y r t i u c r i c e t a t s - 3 l t tf o . o n s n i p 3 2 2 3 p sv 5 . 5 + o t v 0 . 3 +22s r o t i c a p a c 4s e ys e y0 2 3 4 2 3 p sv 5 . 5 + o t v 0 . 3 +35s r o t i c a p a c 4s e ys e y8 2
rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation 2 note 1 : v+ and v- can have maximum magnitudes of 7v, but their absolute difference cannot exceed 13v. absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. v cc .......................................................-0.3v to +6.0v v+ (note 1).......................................-0.3v to +7.0v v- (note 1)........................................+0.3v to -7.0v v+ + |v-| (note 1)...........................................+13v i cc (dc v cc or gnd current)......................... +100ma input voltages txin, online, shutdown, en ( sp3223 ).................-0.3v to +6.0v rxin................................................................... +15v output voltages txout............................................................... +15v rxout, status.......................-0.3v to (v cc + 0.3v) short-circuit duration txout.....................................................continuous storage temperature......................-65 c to +150 c unless otherwise noted, the following specifications apply for v cc = +3.0v to +5.5v with t amb = t min to t max . typical values apply at v cc = +3.3v or +5.0v and t amb = 25 c. specifications r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c s c i t s i r e t c a r a h c c d , t n e r r u c y l p p u s e n i l - n o o t u a 0 . 10 1 a , d n g = e n i l n o , n e p o n i x r l l a v = n w o d t u h s c c v = n i x t , c c r o v , d n g c c t , v 3 . 3 + = b m a c 5 2 + = n w o d t u h s , t n e r r u c y l p p u s0 . 10 1 a v = n i x t , d n g = n w o d t u h s c c r o v , d n g c c t , v 3 . 3 + = b m a c 5 2 + = , t n e r r u c y l p p u s e n i l - n o o t u a d e l b a s i d 3 . 00 . 1a mv = n w o d t u h s = e n i l n o c c , v , d a o l o n c c t , v 3 . 3 + = b m a c 5 2 + = s t u p t u o r e v i e c e r d n a s t u p n i c i g o l d l o h s e r h t c i g o l t u p n i w o l h g i h0 . 2 8 . 0 v v c c n i x t , v 0 . 5 + r o v 3 . 3 + =, ( n e 3 2 2 3 p s , e n i l n o , ) n w o d t u h s t n e r r u c e g a k a e l t u p n i1 0 . 0 ? . 1 a , n w o d t u h s , e n i l n o , n e , n i x t t b m a c 5 2 + = t n e r r u c e g a k a e l t u p t u o5 0 . 0 ? 1 a d e l b a s i d s r e v i e c e r w o l e g a t l o v t u p t u o4 . 0vi t u o a m 6 . 1 = h g i h e g a t l o v t u p t u ov c c 6 . 0 -v c c 1 . 0 -vi t u o a m 0 . 1 - = power dissipation per package 28-pin pdip (derate 16.0mw/ o c above+70 o c).....1300mw 20-pin ssop (derate 9.25mw/ o c above +70 o c).... 750mw 20-pin tssop (derate 11.1mw/ o c above +70 o c)..900mw 28-pin soic (derate 12.7mw/ o c above +70 o c)... 1000mw 28-pin ssop (derate 11.2mw/ o c above +70 o c).... 900mw
3 rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c s t u p t u o r e v i r d g n i w s e g a t l o v t u p t u o0 . 5 ? . 5 ? k 3 h t i w d e d a o l s t u p t u o r e v i r d l l a ? t , d n g o t b m a c 5 2 + = e c n a t s i s e r t u p t u o0 0 3 ? v c c v , v 0 = - v = + v = t u o v 2 = t n e r r u c t i u c r i c - t r o h s t u p t u o5 3 0 7 0 6 0 0 1 a m v t u o v 0 = v t u o =v 5 1 t n e r r u c e g a k a e l t u p t u o5 2 a v c c , v 5 . 5 o t v 0 . 3 r o v 0 = v t u o d e l b a s i d s r e v i r d , v 2 1 = s t u p n i r e v i e c e r e g n a r e g a t l o v t u p n i5 1 -5 1v w o l d l o h s e r h t t u p n i6 . 02 . 1vv c c v 3 . 3 = w o l d l o h s e r h t t u p n i8 . 05 . 1vv c c v 0 . 5 = h g i h d l o h s e r h t t u p n i5 . 14 . 2vv c c v 3 . 3 = h g i h d l o h s e r h t t u p n i8 . 14 . 2vv c c v 0 . 5 = s i s e r e t s y h t u p n i3 . 0v e c n a t s i s e r t u p n i357k ? e n i l - n o o t u a v = n w o d t u h s , d n g = e n i l n o ( s c i t s i r e t c a r a h c y r t i u c r i c c c ) w o l e g a t l o v t u p t u o s u t a t s4 . 0vi t u o a m 6 . 1 = h g i h e g a t l o v t u p t u o s u t a t sv c c 6 . 0 -vi t u o a m 0 . 1 - = s r e v i r d o t d l o h s e r h t r e v i e c e r t ( d e l b a n e e n i l n o ) 0 0 2 s 5 1 e r u g i f e v i t a g e n r o e v i t i s o p r e v i e c e r h g i h s u t a t s o t d l o h s e r h t t ( h s t s ) 5 . 0 s 5 1 e r u g i f e v i t a g e n r o e v i t i s o p r e v i e c e r w o l s u t a t s o t d l o h s e r h t t ( l s t s ) 0 2 s 5 1 e r u g i f specifications (continued) unless otherwise noted, the following specifications apply for v cc = +3.0v to +5.5v with t amb = t min to t max . typical values apply at v cc = +3.3v or +5.0v and t amb = 25 c.
rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation 4 specifications (continued) unless otherwise noted, the following specifications apply for v cc = +3.0v to +5.5v with t amb = t min to t max . typical values apply at v cc = +3.3v or +5.0v and t amb = 25 c. figure 1. transmitter output voltage vs. load capacitance for the sp3223 figure 2. slew rate vs. load capacitance for the sp3223 typical performance characteristics unless otherwise noted, the following performance characteristics apply for v cc = +3.3v, 120kbps data rate, all drivers loaded with 3k ? , 0.1 f charge pump capacitors, and t amb = +25 c. 6 4 2 0 -2 -4 -6 t ransmitter output voltage [v] load capacitance [pf] vo ut+ vo ut- 500 1000 1500 0 14 12 10 8 6 4 2 0 slew rate [v/ s] load capacitance [pf] +slew -slew 0 500 1000 1500 2000 r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c s c i t s i r e t c a r a h c g n i m i t e t a r a t a d m u m i x a m0 2 15 3 2s p b kr l k 3 = ? c , l e v i t c a r e v i r d e n o , f p 0 0 0 1 = y a l e d n o i t a g a p o r p r e v i e c e r t l h p t h l p 3 . 0 3 . 0 sc , t u p t u o r e v i e c e r o t t u p n i r e v i e c e r l f p 0 5 1 = e m i t e l b a n e t u p t u o r e v i e c e r0 0 2s nn o i t a r e p o l a m r o n e m i t e l b a s i d t u p t u o r e v i e c e r0 0 2s nn o i t a r e p o l a m r o n w e k s r e v i r d0 0 10 0 5s nt | l h p t - h l p t , | b m a 5 2 = o c w e k s r e v i e c e r0 0 20 0 0 1s nt | l h p t - h l p | e t a r w e l s n o i g e r - n o i t i s n a r t0 3/ v sv c c r , v 3 . 3 = l k 3 = ? t , b m a 5 2 = o , c r o v 0 . 3 + o t v 0 . 3 - m o r f n e k a t s t n e m e r u s a e m v 0 . 3 - o t v 0 . 3 +
5 rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation figure 3. supply current vs. load capacitance when transmitting data for the sp3223 figure 4. transmitter output voltage vs. load capacitance for the sp3243 figure 5. slew rate vs. load capacitance for the sp3243 figure 6. supply current vs. load capacitance when transmitting data for the sp3243 typical performance characteristics (continued) unless otherwise noted, the following performance characteristics apply for v cc = +3.3v, 120kbps data rate, all drivers loaded with 3k ? , 0.1 f charge pump capacitors, and t amb = +25 c. 40 35 30 25 20 15 10 5 0 supply current [ma] load capacitance [pf] 118khz 60khz 10khz 0 500 1000 1500 2000 6 4 2 0 -2 -4 -6 t ransmitter output voltage [v] load capacitance [pf] v out+ v out- 500 1000 1500 2000 2500 0 16 14 12 10 8 6 4 2 0 slew rate [v/ s] load capacitance [pf] 0 500 1000 1500 2000 2500 3000 + slew - slew 80 70 60 50 40 30 20 10 0 supply current [ma] load capacitance [pf] 0 500 1000 1500 2000 2500 118khz 60khz 10khz 3000
rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation 6 table 1. device pin description e m a nn o i t c n u f r e b m u n n i p 3 2 2 3 p s3 4 2 3 p s n e h g i h c i g o l y l p p a . n o i t a r e p o l a m r o n r o f w o l c i g o l y l p p a . e l b a n e r e v i e c e r . ) e t a t s z - h g i h ( s t u p t u o r e v i e c e r e h t e l b a s i d o t 1- + 1 c . r o t i c a p a c p m u p - e g r a h c r e l b u o d e g a t l o v e h t f o l a n i m r e t e v i t i s o p 28 2 + v. p m u p e g r a h c e h t y b d e t a r e n e g t u p t u o v 5 . 5 + d e t a l u g e r 37 2 - 1 c . r o t i c a p a c p m u p - e g r a h c r e l b u o d e g a t l o v e h t f o l a n i m r e t e v i t a g e n 44 2 + 2 c. r o t i c a p a c p m u p - e g r a h c g n i t r e v n i e h t f o l a n i m r e t e v i t i s o p 51 - 2 c. r o t i c a p a c p m u p - e g r a h c g n i t r e v n i e h t f o l a n i m r e t e v i t a g e n 62 - v. p m u p e g r a h c e h t y b d e t a r e n e g t u p t u o v 5 . 5 - d e t a l u g e r 73 r 1 n i. t u p n i r e v i e c e r 2 3 2 - s r 6 14 r 2 n i. t u p n i r e v i e c e r 2 3 2 - s r 95 r 3 n i. t u p n i r e v i e c e r 2 3 2 - s r -6 r 4 n i. t u p n i r e v i e c e r 2 3 2 - s r -7 r 5 n i. t u p n i r e v i e c e r 2 3 2 - s r -8 r 1 t u o. t u p t u o r e v i e c e r s o m c / l t t 5 19 1 r 2 t u o. t u p t u o r e v i e c e r s o m c / l t t 0 18 1 r 2 t u o. n w o d t u h s n i e v i t c a , t u p t u o 2 - r e v i e c e r g n i t r e v n i - n o n -0 2 r 3 t u o. t u p t u o r e v i e c e r s o m c / l t t -7 1 r 4 t u o. t u p t u o r e v i e c e r s o m c / l t t -6 1 r 5 t u o. t u p t u o r e v i e c e r s o m c / l t t -5 1 s u t a t s. s u t a t s n w o d t u h s d n a e n i l n o g n i t a c i d n i t u p t u o s o m c / l t t 1 11 2 t 1 n i. t u p n i r e v i r d s o m c / l t t 3 14 1 t 2 n i. t u p n i r e v i r d s o m c / l t t 2 13 1 t 3 n i. t u p n i r e v i r d s o m c / l t t -2 1 e n i l n o e d i r r e v o o t h g i h c i g o l y l p p a e n i l - n o o t u a s r e v i r d g n i p e e k y r t i u c r i c . ) 2 e l b a t o t r e f e r , h g i h c i g o l e b o s l a t s u m n w o d t u h s ( e v i t c a 4 13 2 t 1 t u o. t u p t u o r e v i r d 2 3 2 - s r 7 19 t 2 t u o. t u p t u o r e v i r d 2 3 2 - s r 80 1 t 3 t u o. t u p t u o r e v i r d 2 3 2 - s r -1 1 d n g. d n u o r g 8 15 2 v c c . e g a t l o v y l p p u s v 5 . 5 + o t v 0 . 3 + 9 16 2 n w o d t u h s l l a s e d i r r e v o s i h t . p m u p e g r a h c d n a s r e v i r d n w o d t u h s o t w o l c i g o l y l p p a e n i l - n o o t u a . ) 2 e l b a t o t r e f e r ( e n i l n o d n a y r t i u c r i c 0 22 2
7 rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation figure 8. sp3243 pinout configuration figure 7. sp3223 pinout configuration v- 1 2 3 4 17 18 19 20 5 6 7 16 15 14 shutdown c1+ v+ c1- c2+ c2- online en r 1 in gnd v cc t 1 out status 8 9 10 11 12 13 r 2 in r 2 out sp3223 t 2 out t 1 in t 2 in r 1 out r 4 in 1 2 3 4 25 26 27 28 5 6 7 24 23 22 shutdown c2- v- r 1 in r 2 in r 3 in online c2+ c1- gnd v cc v+ status t 1 in 8 9 10 11 18 19 20 21 12 13 14 17 16 15 r 5 out t 1 out t 2 out t 3 out t 3 in t 2 in r 4 out r 5 in r 3 out r 2 out r 1 out r 2 out sp3243 c1+
rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation 8 figure 9. sp3223 typical operating circuit sp3223 2 4 6 5 3 7 19 gnd t 1 in t 2 in c1+ c1- c2+ c2- v+ v- v cc 13 12 0.1 f 0.1 f 0.1 f + c2 c5 c1 + + c3 c4 + + 0.1 f 0.1 f 17 8 rs-232 outputs rs-232 inputs ttl/cmos inputs +3v to +5v 18 shutdown 20 5k ? r 1 out 15 16 5k ? r 2 in r 2 out 10 9 ttl/cmos outputs en 1 online 14 r 1 in t 2 out t 1 out 11 status v cc to p supervisor circuit
9 rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation figure 10. sp3243 typical operating circuit sp3243 28 24 2 1 27 3 26 5k ? 5k ? 5k ? 5k ? 5k ? gnd c1+ c1- c2+ c2- v+ v- v cc 14 13 12 20 19 18 17 16 15 0.1 f 0.1 f 0.1 f + c2 c5 c1 + + c3 c4 + + 0.1 f 0.1 f 9 10 11 4 5 6 7 8 rs-232 outputs rs-232 inputs ttl/cmos inputs ttl/cmos outputs to p supervisor circuit 23 22 21 v cc v cc 25 t 1 in r 1 out r 1 in t 2 out r 2 out t 2 in t 3 in t 3 out t 1 out r 2 in r 3 in r 4 in r 5 in r 2 out r 3 out r 4 out r 5 out online shutdown status
rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation 10 description the sp3223 and sp3243 transceivers meet the eia/tia-232 and itu-t v.28/v.24 communica- tion protocols and can be implemented in bat- tery-powered, portable, or hand-held applica- tions such as notebook or palmtop computers. the sp3223 and sp3243 devices feature sipex's proprietary and patented (u.s.-- 5,306,954) on- board charge pump circuitry that generates 5.5v rs-232 voltage levels from a single +3.0v to +5.5v power supply. the sp3223 and sp3243 devices can operate at a typical data rate of 235kbps fully loaded. the sp3223 is a 2-driver/2-receiver device, and the sp3243 is a 3-driver/5-receiver device ideal for portable or hand-held applications. the sp3243 includes one complementary always-active receiver that can monitor an external device (such as a modem) in shutdown. this aids in protecting the uart or serial controller ic by preventing forward biasing of the protection diodes where v cc may be disconnected. the sp3223 and sp3243 series is an ideal choice for power sensitive designs. the sp3223 and sp3243 devices feature auto on-line circuitry which reduces the power supply drain to a 1 a supply current. in many portable or hand-held applications, an rs-232 cable can be disconnected or a connected peripheral can be turned off. under these conditions, the internal charge pump and the drivers will be shut down. otherwise, the system automatically comes online. this feature allows design engineers to address power saving concerns without major design changes. theory of operation the sp3223 and sp3243 series is made up of four basic circuit blocks: 1. drivers, 2. receivers, 3. the sipex proprietary charge pump, and 4. auto on-line cir- cuitry. drivers the drivers are inverting level transmitters that convert ttl or cmos logic levels to 5.0v eia/ tia-232 levels with an inverted sense relative to the input logic levels. typically, the rs-232 output voltage swing is + 5.4v with no load and + 5v minimum fully loaded. the driver outputs are protected against infinite short-circuits to ground without degradation in reliability. these drivers comply with the eia-tia-232f and all previous rs-232 versions. unused driver inputs should be connected to gnd or v cc . the drivers can guarantee a data rate of 120kbps fully loaded with 3k ? in parallel with 1000pf, ensuring compatibility with pc-to-pc commu- nication software. the slew rate of the driver output is internally limited to a maximum of 30v/ s in order to meet the eia standards (eia rs-232d 2.1.7, paragraph 5). the transition of the loaded output from high to low also meets the monotonicity requirements of the standard. figure 11. interface circuitry controlled by micropro- cessor supervisory circuit sp3243 28 24 2 1 27 3 26 5k ? 5k ? 5k ? 5k ? 5k ? gnd c1+ c1- c2+ c2- v+ v- v cc 14 13 12 20 19 18 17 16 15 0.1 f 0.1 f 0.1 f + c2 c5 c1 + + c3 c4 + + 0.1 f 0.1 f 9 10 11 4 5 6 7 8 rs-232 outputs rs-232 inputs 23 22 21 v cc 25 t 1 in r 1 out r 1 in t 2 out r 2 out t 2 in t 3 in t 3 out t 1 out r 2 in r 3 in r 4 in r 5 in r 2 out r 3 out r 4 out r 5 out online shutdown status uart or serial c p supervisor ic txd rts dtr rxd cts dsr dcd ri v cc v in reset
11 rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation figure 12 shows a loopback test circuit used to test the rs-232 drivers. figure 13 shows the test results of the loopback circuit with all three drivers active (sp3243) at 120kbps with typical rs-232 loads in parallel with 1000pf capacitors. figure 14 shows the test results where one driver was active at 235kbps and all three drivers loaded with an rs-232 receiver in parallel with a 1000pf capacitor. a solid rs-232 data trans- table 2. shutdown and en truth tables note: in auto on-line mode where online = gnd and shutdown = v cc , the device will shut down if there is no activity present at the receiver inputs. figure 12. loopback test circuit for rs-232 driver data transmission rates mission rate of 120kbps provides compatibility with many designs in personal computer periph- erals and lan applications. receivers the receivers convert 5.0v eia/tia-232 levels to ttl or cmos logic output levels. receivers have an inverting output that can be disabled by using the en pin. figure 13. loopback test circuit result at 120kbps (all drivers fully loaded) figure 14. loopback test circuit result at 235kbps (all drivers fully loaded) sp3223 sp3243 2 4 6 5 3 7 19 gnd t 1 in t x in c1+ c1- c2+ c2- v+ v- v cc 0.1 f 0.1 f 0.1 f + c2 c5 c1 + + c3 c4 + + 0.1 f 0.1 f ttl/cmos inputs +3v to +5v 18 shutdown 20 5k ? r 1 out 5k ? r x in r x out ttl/cmos outputs en 1 online 14 r 1 in t x out t 1 out 11 status v cc to p supervisor circuit 1000pf 1000pf 3 2 2 3 p s : e c i v e d n w o d t u h sn et x t u or x t u o 00 z h g i he v i t c a 01 z h g i hz h g i h 10 e v i t c ae v i t c a 11 e v i t c az h g i h 3 4 2 3 p s : e c i v e d n w o d t u h st x t u or x t u or 2 t u o 0z h g i hz h g i he v i t c a 1e v i t c ae v i t c ae v i t c a t1 in t1 out r1 out t1 in t1 out r1 out
rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation 12 receivers are active when the auto on-line circuitry is enabled or when in shutdown. during the shutdown, the receivers will continue to be active. if there is no activity present at the receivers for a period longer than 100 s or when shutdown is enabled, the device goes into a standby mode where the circuit draws 1 a. driving en to a logic high forces the outputs of the receivers into high-impedance. the truth table logic of the sp3223 and sp3243 driver and receiver outputs can be found in table 2 . the sp3243 includes an additional non-invert- ing receiver with an output r 2 out. r 2 out is an extra output that remains active and monitors activity while the other receiver outputs are forced into high impedance. this allows ring indicator (ri) from a peripheral to be monitored without forward biasing the ttl/cmos inputs of the other devices connected to the receiver outputs. since receiver input is usually from a transmis- sion line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 300mv. this ensures that the receiver is virtually immune to noisy transmission lines. should an input be left unconnected, an internal 5k ? pulldown resistor to ground will commit the output of the receiver to a high state. charge pump the charge pump is a sipex ?atented design (u.s. 5,306,954) and uses a unique approach compared to older less?fficient designs. the charge pump still requires four external capacitors, but uses a four?hase voltage shifting technique to attain symmetrical 5.5v power supplies. the internal power supply consists of a regulated dual charge pump that provides output voltages 5.5v regardless of the input voltage (v cc ) over the +3.0v to +5.5v range. this is important to maintain compliant rs-232 levels regardless of power supply fluctuations. the charge pump operates in a discontinuous mode using an internal oscillator. if the output voltages are less than a magnitude of 5.5v, the charge pump is enabled. if the output voltages exceed a magnitude of 5.5v, the charge pump is disabled. this oscillator controls the four phases of the voltage shifting. a description of each phase follows. phase 1 ?v ss charge storage ?during this phase of the clock cycle, the positive side of capacitors c 1 and c 2 are initially charged to v cc . c l + is then switched to gnd and the charge in c 1 is transferred to c 2 . since c 2 + is connected to v cc , the voltage potential across capacitor c 2 is now 2 times v cc . phase 2 ?v ss transfer ?phase two of the clock connects the negative terminal of c 2 to the v ss storage capacitor and the positive terminal of c 2 to gnd. this transfers a negative generated voltage to c 3 . this generated voltage is regulated to a minimum voltage of -5.5v. simultaneous with the transfer of the voltage to c 3 , the positive side of capacitor c 1 is switched to v cc and the negative side is connected to gnd. phase 3 ?v dd charge storage ?the third phase of the clock is identical to the first phase ?the charge transferred in c 1 produces ? cc in the negative terminal of c 1 , which is applied to the negative side of capacitor c 2 . since c 2 + is at v cc , the voltage potential across c 2 is 2 times v cc . phase 4 ?v dd transfer ?the fourth phase of the clock connects the negative terminal of c 2 to gnd, and transfers this positive generated voltage across c 2 to c 4 , the v dd storage capacitor. this voltage is regulated to +5.5v. at this voltage, the internal oscillator is disabled. simultaneous with the transfer of the voltage to c 4 , the positive side of capacitor c 1 is switched to v cc and the negative side is connected to gnd, allowing the charge pump cycle to begin again. the charge pump cycle will continue as long as the operational conditions for the internal oscillator are present.
13 rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation since both v + and v are separately generated from v cc , in a no?oad condition v + and v will be symmetrical. older charge pump approaches that generate v from v + will show a decrease in the magnitude of v compared to v + due to the inherent inefficiencies in the design. figure 15. auto on-line timing waveforms receiver rs-232 input voltages status +5v 0v -5v t stsl t stsh t online v cc 0v driver rs-232 output vo ltages 0v +2.7v -2.7v s h u t d o w n the clock rate for the charge pump typically operates at 250khz. the external capacitors can be as low as 0.1 f with a 16v breakdown voltage rating.
rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation 14 figure 17. charge pump ?phase 2 figure 18. charge pump waveforms v cc = +5v ?0v v ss storage capacitor v dd storage capacitor c 1 c 2 c 3 c 4 + + ++ figure 19. charge pump ?phase 3 v cc = +5v ?v +5v ?v v ss storage capacitor v dd storage capacitor c 1 c 2 c 3 c 4 + + ++ figure 20. charge pump ?phase 4 v cc = +5v +10v v ss storage capacitor v dd storage capacitor c 1 c 2 c 3 c 4 + + ++ v cc = +5v ?v ?v +5v v ss storage capacitor v dd storage capacitor c 1 c 2 c 3 c 4 + + ++ figure 16. charge pump ?phase 1 ch1 2.00v ch2 2.00v m 1.00 s ch1 1.96v 2 1 t t [] t 2 +6v a) c 2+ b) c 2 - -6v 0v 0v
15 rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation figure 21. sp3243 driver output voltages vs. load current per transmitter figure 22. circuit for the connectivity of the sp3243 with a db-9 connector 6 4 2 0 -2 -4 -6 tr ansmitter output voltage [v] load current per transmitter [ma] v out+ v out- 0.62 0.869 0.939 1.02 1.12 1.23 1.38 1.57 1.82 2.67 3.46 4.93 8.6 6 7 8 9 1 2 3 4 5 db-9 connector 6. dce ready 7. request to send 8. clear to send 9. ring indicator db-9 connector pins: 1. received line signal detector 2. received data 3. transmitted data 4. data terminal ready 5. signal ground (common) sp3243 28 24 2 1 27 3 26 5k ? 5k ? 5k ? 5k ? 5k ? gnd c1+ c1- c2+ c2- v+ v- v cc 14 13 12 20 19 18 17 16 15 0.1 f 0.1 f 0.1 f + c2 c5 c1 + + c3 c4 + + 0.1 f 0.1 f 9 10 11 4 5 6 7 8 to p supervisor circuit 23 22 21 v cc v cc 25 t 1 in r 1 out r 1 in t 2 out r 2 out t 2 in t 3 in t 3 out t 1 out r 2 in r 3 in r 4 in r 5 in r 2 out r 3 out r 4 out r 5 out online shutdown status
rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation 16 table 3. auto on-line logic figure 23. stage i of auto on-line circuitry figure 24. stage ii of auto on-line circuitry l a n g i s 2 3 2 - s r r e v i e c e r t a t u p n i n w o d t u h s t u p n i t u p n i e n i l n ot u p t u o s u t a t s r e v i e c s n a r t s u t a t s s e yh g i hw o lh g i h n o i t a r e p o l a m r o n e n i l - n o o t u a ( ) o nh g i hh g i hw o l n o i t a r e p o l a m r o n o nh g i hw o lw o l n w o d t u h s e n i l - n o o t u a ( ) s e yw o lw o l / h g i hh g i h n w o d t u h s o nw o lw o l / h g i hw o l n w o d t u h s rs-232 receiver block r x inact inactive detection block r x in r x out r 1 inact r 2 inact r 3 inact r 4 inact r 5 inact delay stage delay stage delay stage delay stage delay stage shutdown status
17 rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation auto on-line circuitry the sp3223 and sp3243 devices have a patent pending auto on-line circuitry on board that saves power in applications such as laptop computers, palmtop (pda) computers, and other portable systems. the sp3223 and sp3243 devices incorporate an auto on-line circuit that automatically enables itself when the external transmitters are enabled and the cable is connected. conversely, the auto on-line ? circuit also disables most of the internal circuitry when the device is not being used and goes into a standby mode where the device typically draws 1 a. this function can also be externally controlled by the online pin. when this pin is tied to a logic low, the auto on-line function is active. once active, the device is enabled until there is no activity on the receiver inputs. the receiver input typically sees at least 3v, which are generated from the transmitters at the other end of the cable with a 5v minimum. when the external transmitters are disabled or the cable is disconnected, the receiver inputs will be pulled down by their internal 5k ? resistors to ground. when this occurs over a period of time, the internal transmitters will be disabled and the device goes into a shutdown or standy mode. when online is high, the auto on-line mode is disabled. the auto on-line circuit has two stages: 1) inactive detection 2) accumulated delay the first stage, shown in figure 23 , detects an inactive input. a logic high is asserted on r x inact if the cable is disconnected or the external transmitters are disabled. otherwise, r x inact will be at a logic low. this circuit is duplicated for each of the other receivers. the second stage of the auto on-line circuitry, shown in figure 24 , processes all the receiver's r x inact signals with an accumu- lated delay that disables the device to a 1 a supply current. the status pin goes to a logic low when the cable is disconnected, the external transmitters are disabled, or the shutdown pin is invoked. the typical accumulated delay is around 20 s. when the sp3223 and sp3243 drivers or inter- nal charge pump are disabled, the supply current is reduced to 1 a. this can commonly occur in hand-held or portable applications where the rs-232 cable is disconnected or the rs-232 drivers of the connected peripheral are turned off. the auto on-line mode can be disabled by the shutdown pin. if this pin is a logic low,the auto on-line function will not operate regardless of the logic state of the online pin. table 3 summarizes the logic of the auto on-line operating modes. the truth table logic of the sp3223 and sp3243 driver and receiver outputs can be found in table 2. the status pin outputs a logic low signal if the device is shutdown. this pin goes to a logic high when the external transmitters are enabled and the cable is connected. when the sp3223 and sp3243 devices are shut down, the charge pumps are turned off. v+ charge pump output decays to v cc , the v- output decays to gnd. the decay time will depend on the size of capacitors used for the charge pump. once in shutdown, the time required to exit the shut down state and have valid v+ and v- levels is typically 200 s. for easy programming, the status can be used to indicate dtr or a ring indicator signal. tying online and shutdown together will bypass the auto on-line circuitry so this connection acts like a shutdown input pin.
rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation 18 esd tolerance the sp3223/3243 series incorporates ruggedized esd cells on all driver output and receiver input pins. the esd structure is improved over our previous family for more rugged applications and environments sensitive to electro-static discharges and associated transients. the human body model has been the generally accepted esd testing method for semiconductors. this method is also specified in mil-std-883, method 3015.7 for esd testing. the premise of this esd test is to simulate the human body? potential to store electro-static energy and discharge it to an integrated circuit. the simulation is performed by using a test model as shown in figure 25 . this method will test the ic? capability to withstand an esd transient during normal handling such as in manufacturing areas where the ics tend to be handled frequently. for the human body model, the current limiting resistor (r s ) and the source capacitor (c s ) are 1.5k ? and 100pf, respectively. r c c s r s sw1 sw2 r c device under t est dc power source c s r s sw1 sw2 figure 25. esd test circuit for human body model
19 rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation d alternate end pins (both ends) d1 = 0.005" min. (0.127 min.) e package: plastic dual?n?ine (narrow) dimensions (inches) minimum/maximum (mm) a = 0.210" max. (5.334 max). e1 c l a2 a1 = 0.015" min. (0.381min.) b b1 e = 0.100 bsc (2.540 bsc) e a = 0.300 bsc (7.620 bsc) a2 b b1 c d e e1 l 16?in 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.780/0.800 (19.812/20.320) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15 (0?15? 20?in 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.980/1.060 (24.892/26.924) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15 (0?15? 28?in 0.068/0.078 (1.73/1.99) 0.002/0.008 (0.05/0.21) 0.010/0.015 (0.25/0.38) 0.397/0.407 (10.07/10.33) 0.205/0.212 (5.20/5.38) 0.0256 bsc (0.65 bsc) 0.301/0.311 (7.65/7.90) 0.022/0.037 (0.55/0.95) 0?8 (0?8?
rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation 20 d eh package: plastic shrink small outline (ssop) dimensions (inches) minimum/maximum (mm) 20?in a a1 l b e a a1 b d e e h l 0.068/0.078 (1.73/1.99) 0.002/0.008 (0.05/0.21) 0.010/0.015 (0.25/0.38) 0.278/0.289 (7.07/7.33) 0.205/0.212 (5.20/5.38) 0.0256 bsc (0.65 bsc) 0.301/0.311 (7.65/7.90) 0.022/0.037 (0.55/0.95) 0?8 (0?8? 24?in 0.068/0.078 (1.73/1.99) 0.002/0.008 (0.05/0.21) 0.010/0.015 (0.25/0.38) 0.317/0.328 (8.07/8.33) 0.205/0.212 (5.20/5.38) 0.0256 bsc (0.65 bsc) 0.301/0.311 (7.65/7.90) 0.022/0.037 (0.55/0.95) 0?8 (0?8? 28?in 0.068/0.078 (1.73/1.99) 0.002/0.008 (0.05/0.21) 0.010/0.015 (0.25/0.38) 0.397/0.407 (10.07/10.33) 0.205/0.212 (5.20/5.38) 0.0256 bsc (0.65 bsc) 0.301/0.311 (7.65/7.90) 0.022/0.037 (0.55/0.95) 0?8 (0?8? 16?in 0.068/0.078 (1.73/1.99) 0.002/0.008 (0.05/0.21) 0.010/0.015 (0.25/0.38) 0.239/0.249 (6.07/6.33) 0.205/0.212 (5.20/5.38) 0.0256 bsc (0.65 bsc) 0.301/0.311 (7.65/7.90) 0.022/0.037 (0.55/0.95) 0?8 (0?8?
21 rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation d eh package: plastic small outline (soic) (wide) dimensions (inches) minimum/maximum (mm) a a1 l b e a a1 b d e e h l 28?in 0.093/0.104 (2.352/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.697/0.713 (17.70/18.09) 0.291/0.299 (7.402/7.600) 0.050 bsc (1.270 bsc) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0?8 (0?8?
rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation 22 pa ckage: plastic thin small outline (tssop) dimensions in inches (mm) minimum/maximum a a1 l b e a a1 b d e e e2 l e2 d - /0.043 (- /1.10) 0.002/0.006 (0.05/0.15) 0.007/0.012 (0.19/0.30) 0.252/0.260 (6.40/6.60) 0.169/0.177 (4.30/4.50) 0.026 bsc (0.65 bsc) 0.126 bsc (3.20 bsc) 0.020/0.030 (0.50/0.75) 0 /8 20?in e
23 rev. 6/30/03 sp3223 +3.0v to +5.5v rs-232 transceivers ?copyright 2003 sipex corporation model temperature range package types sp3223cp 0 c to +70 c 20-pin pdip sp3223ca 0 c to +70 c 20-pin ssop sp3223cy 0? to +70? 20-pin tssop sp3223ep -40 c to +85 c 20-pin pdip sp3223ea -40 c to +85 c 20-pin ssop SP3223EY -40 c to +85 c 20-pin tssop sp3243ct 0 c to +70 c 28-pin wide soic sp3243ca 0 c to +70 c 28-pin ssop sp3243et -40 c to +85 c 28-pin wide soic sp3243ea -40 c to +85 c 28-pin ssop ordering information corporation analog excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability aris ing out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. please consult the factory for pricing and availability on a tape-on-reel option. sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 sales office 22 linnell circle billerica, ma 01821 tel: (978) 667-8700 fax: (978) 670-9001 e-mail: sales@sipex.com

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